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This article delves into the technical aspects of how scaling up and out is becoming a critical need for HPC and AI chip developers, and how new standards such as Ultra Ethernet and Ultra Accelerator Link UALink aim to tackle the challenges of high-bandwidth, low-latency connectivity and efficient resource management. Emergence of new standards

This year, we are getting the Ultra Accelerator Link or UALink to target NVLink. UALink will be the Open NVLink Competitor. First off, this call was put together by AMD, but it was also attended by folks from companies like Intel and Broadcom. As part of the promoter group, Cisco, Google, HPE, Meta, and Microsoft were also onboard.

Ultra Accelerator Link UALink is an open specification for a die-to-die interconnect and serial bus between AI accelerators.It is co-developed by Alibaba, AMD, Apple, Astera Labs, 1 AWS, Cisco, Google, Hewlett Packard Enterprise, Intel, Meta, Microsoft and Synopsys. 2UALink officially incorporated as an organization in 2024, and its first specification will provide interconnectivity

Enter Ultra Accelerator Link TM or UALink TM for short. UALink is an open industry standard for a memory semantic, scale-up fabric protocol developed by the UALink Consortium. The specification enables load, store, and atomic operations between 100s of GPUs while optimizing the protocol stack to minimize end-to-end latency, reducing valuable

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UALink, or Ultra Accelerator Link, is an open-standard technology developed as an open alternative to NVIDIA's proprietary NVLink. It focuses on enhancing GPU interconnectivity for high-performance computing and AI applications, supporting up to 1,024 accelerators in a shared memory pod by Q3 2024, with further enhancements planned.

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AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft have joined forces to develop Ultra Accelerator Link UALink, a new industry standard to enable high-speed, low-latency

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